I am at the Graduate School of Information, Production and Systems, Waseda University. My research focuses on emerging-memory-based neural network accelerators, Hardware-Conscious Software Training (HCST), and energy-efficient neuromorphic computing.

My published work spans hardware-conscious training for analog DNN inference accelerators, STT-MTJ device modeling, and the structural evolution of spiking neural networks.

I am particularly interested in:

Analog / mixed-signal computing-in-memory (CIM)
Hardware-software co-design for AI accelerators
High energy-efficiency architectures for edge intelligence

📝 Publications

JJAP 2024

Double-crossbar DNN synapse array and neuron circuits from SSDM 2023 Figure 1

Related architecture: Gao & Ohsawa, SSDM 2023, Fig. 1 (author manuscript).

A training method for deep neural network inference accelerators with high tolerance for their hardware imperfection

Shuchao Gao, Takashi Ohsawa

Paper · Project

We have proposed an algorithm (software) method to address the offset voltage issue of operational amplifier in DNN inference accelerators in advanced process. This method is verified in a larger dataset.
Fully Analog ReRAM Inference Accelerator: An open-source framework for exploring fully analog ReRAM inference accelerators that avoid repeated inter-layer ADC/DAC conversions. It models ReRAM synapse arrays and analog neuron circuits for current-to-voltage conversion, subtraction, activation, and inter-layer driving. Finite-gain and offset models, together with hardware-conscious training tools, support studies of how circuit nonidealities affect inference accuracy.

SSDM 2023

Hardware-conscious software training with hardware emulator, backpropagation and hardware inference

Gao & Ohsawa, SSDM 2023, Fig. 5 (author manuscript).

Hardware-conscious Software Training for Deep Neural Network Inference Accelerator Chips to Recover Accuracy Degradation due to Hardware Variabilities

Shuchao Gao, Takashi Ohsawa

Paper · arXiv version

Presented at SSDM 2023.

We have proposed an algorithm (software) method to address the offset voltage issue of operational amplifier in DNN inference accelerators in advanced process. This method is verified in IRIS dataset.

Hardware-conscious Training for Deep Neural Network Inference Accelerators to Restore Accuracy Degradation due to Hardware Imperfection

ISIPS 2023

Shuchao Gao, Takashi Ohsawa

We have designed a hardware training algorithm that can significantly improve the accuracy of DNN inference accelerators, even under the effect of the hardware imperfection introduced during the fabrication process. We compared offline training, in-situ training and on-chip training, and proved that hardware-conscious training is the best choice, which makes the non-volatile memory devices free from the endurance constraint, the nonlinearity and the asymmetry issues in updating the resistances.

Single Crossbar Array Architecture for High Density and Low Power Artificial Neural Network

ISIPS 2019

Shuchao Gao, Takashi Ohsawa

We compared three different crossbar array structures to realize negative weight and introduced their training method. We used the Iris dataset to test and train the CBA. We also mathematically derive a single CBA training algorithm. It’s proved that single CBA can be more easily implemented in ReRAM CBA with lower error rate and more stability.

Training ReRAM Crossbar Array in Deep Neural Network

IEICE 2019

Shuchao Gao, Takashi Ohsawa

We proposed a DNN training method to train ReRAM Crossbar Array (CBA). We designed and evaluated the Double Crossbar Array and Single Crossbar Array used to achieve negative weights, which also can perform complex matric multiplication at once only by the basic Ohm’s law and Kirchhoff’s Law.

MEJ 2026